1. Field of the Invention
The present invention relates to a method for fabricating a dynamic random access memory (DRAM) cell, and mole particularly, to a method for fabricating a DRAM cell, capable of obtaining an increased threshold voltage of a metal oxide semiconductor field effect transistor (MOSFET) of the DRAM cell, minimizing current leakage and punchthrough phenomenons between adjacent active legions, and increasing the number of unit chips two times by carrying out a lightly doped drain ion implantation in a specific DRAM cell structure for lightly doping a drain while eliminating a high concentration ion implantation.
2. Description of the Prior Art
Generally, high integration of a DRAM inevitably involves a reduction in chip area and a reduction in cell area. However, such a reduction is difficult to achieve with existing equipment. Despite the development of sophisticated techniques, it has only been possible to achieve a limited reduction in cell area.
A conventional method for fabricating a DRAM will be briefly described. First, a field oxide film is formed on a semiconductor substrate. Thereafter, growth of a gate oxide film is carried out. Over the resulting structure, a polysilicon film is deposited. Following the deposition of the polysilicon film, an impurity implantation is carried out to form a gate electrode and a wold line pattern. Subsequently, formation of a MOSFET is carried out. The MOSFET has an active region formed with a lightly doped drain structure by use of a spacer oxide film in order to improve an electrical characteristic thereof. Over the entire exposed surface of the resulting structure, an insulating oxide film is then deposited to a predetermined thickness. The insulating oxide film is selectively etched so that a contact hole is formed at the drain region of the MOSFET. Thereafter, a doped polysilicon layer or a polycide layer is deposited in the contact hole such that it is in contact with the drain region of the MOSFET. Also, formation of a bit line electrode having a predetermined dimension is formed using a mask. Over the entire exposed surface of the resulting structure, an insulating oxide film is then deposited to a predetermined thickness. The insulating oxide film is selectively etched so that a contact hole is formed at the source region of the MOSFET. Thereafter, a doped polysilicon layer is deposited in the contact hole such that it is in contact with the source region of the MOSFET. Also, formation of a storage electrode having a predetermined dimension is formed using a mask. Subsequently, a dielectric film is grown over the storage electrode. The dielectric film has a composite structure such as a nitride-oxide (NO) composite structure or an oxide-nitride-oxide (ONO) composite structure. Over the entire exposed surface of the resulting structure, a doped polysilicon layer is then formed. The polysilicon layer is patterned to form a plate electrode. Thus, a DRAM is fabricated.
As the integrated semiconductor device fabricated in the above-mentioned manner has a higher integration degree, it becomes more difficult to fabricate such integrated semiconductor device when the existing process capability is taken into consideration.